ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy

• Published in: IEEE transactions on electron devices Vol. 69; no. 9; pp. 5357 - 5362
• Main Authors: Chen, Wen-Chieh, Chen, Shih-Hung, Chiarella, Thomas, Hellings, Geert, Linten, Dimitri, Groeseneken, Guido
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bulk FinFET; Clamping; Electric potential; electrostatic discharge (ESD); Electrostatic discharges; Epitaxial growth; Epitaxy; Field effect transistors; FinFETs; grounded-gate NMOS (ggNMOS); Logic gates; Metal oxide semiconductors; MOSFETs; power-rail ESD clamp; Reliability; Semiconductor devices; Silicon; Static electricity; Stress; Transient response; transmission line pulse (TLP); very-fast transmission line pulse (vfTLP); Voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3190822

In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length (<inline-formula> <tex-math notation="LaTeX">{L}_{g} </tex-math></inline-formula>) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large <inline-formula> <tex-math notation="LaTeX">{L}_{g} </tex-math></inline-formula> effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with <inline-formula> <tex-math notation="LaTeX">{L}_{g} </tex-math></inline-formula> and GPs. With the same gate space, the short <inline-formula> <tex-math notation="LaTeX">{L}_{g} </tex-math></inline-formula> device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance.