A safe programmable electronic system

A dual-channel computer architecture for utilisation in programmable logic controllers is presented. Faults can be detected by novel high-speed comparators with fail-safe operation. The cyclic operating mode of PLCs and a specification-level, graphical programming paradigm based on the interconnecti...

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Bibliographic Details
Published inBulletin of the Polish Academy of Sciences. Technical sciences Vol. 58; no. 3; pp. 423 - 434
Main Authors Halang, W., Śnieżek, M.
Format Journal Article
LanguageEnglish
French
German
Published Warsaw Versita 01.09.2010
Polish Academy of Sciences
Subjects
fail-safe comparison
function block programming
programmable electronic systems
safety
software verification
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Summary:A dual-channel computer architecture for utilisation in programmable logic controllers is presented. Faults can be detected by novel high-speed comparators with fail-safe operation. The cyclic operating mode of PLCs and a specification-level, graphical programming paradigm based on the interconnection of application-oriented standard software function modules are architecturally supported. Thus, by design, there is no semantic gap between the programming and machine execution levels enabling the safety licensing of application software by an extremely simple, but rigorous method, viz., diverse back translation.
Bibliography:v10175-010-0040-4.pdf
ArticleID:v10175-010-0040-4
istex:74D89AC284A398A7AB1289BFF39D0D3A3A7E49AA
ark:/67375/QT4-P3382KCP-4
ISSN:0239-7528
2300-1917
DOI:10.2478/v10175-010-0040-4