Extremely scaled 3-dimensional multiple-gate technologies for terabit era

In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel eff...

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Bibliographic Details
Published inJournal of nanoscience and nanotechnology Vol. 7; no. 11; p. 4126
Main Authors Choi, Yang-Kyu, Kim, Kuk-Hwan, Han, Jin-Woo, Ryu, Seong-Wan, Lee, Hyunjin
Format Journal Article
LanguageEnglish
Published United States 01.11.2007
Subjects
Computer Simulation
Electrons
Equipment Design
Equipment Failure Analysis
Models, Theoretical
Nanotechnology - instrumentation
Nanotechnology - methods
Signal Processing, Computer-Assisted - instrumentation
Transistors, Electronic
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Summary:In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time.
ISSN:1533-4880
DOI:10.1166/jnn.2007.18088