Overlay Mitigation in RTO Process

Across wafer thermal gradients induce distortions that may cause large overlay issues in subsequent lithography process. Misalignment between the gate capacitor and deep trench results in a small contact landing area and much higher contact resistance, impacting the subsequent die yield, especially...

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Bibliographic Details
Published inECS transactions Vol. 44; no. 1; pp. 653 - 656
Main Authors Zhou, Qinggang, Tang, Ji Yue, Zhao, Ganming
Format Journal Article
LanguageEnglish
Published The Electrochemical Society, Inc 16.03.2012
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Summary:Across wafer thermal gradients induce distortions that may cause large overlay issues in subsequent lithography process. Misalignment between the gate capacitor and deep trench results in a small contact landing area and much higher contact resistance, impacting the subsequent die yield, especially in the wafer edge area. Product wafer distortion induced by center and edge temperature differences have a small process window at high temperature and thus are a challenge to control. The isolated and dense areas also have different emissivities generating thermal non-uniformity compared to a blanket wafer. Systematic methods were tested to improve the overlay performance. Adjustment of the edge temperature offset can be used to optimize the high temperature step, greatly minimizing the overlay issues.
ISSN:1938-5862
1938-6737
DOI:10.1149/1.3694383