srNAND: A Novel NAND Flash Organization for Enhanced Small Read Throughput in SSDs

• Published in: IEEE computer architecture letters Vol. 24; no. 2; pp. 197 - 200
• Main Authors: Lee, Jeongho, Kim, Sangjun, Lee, Jaeyong, Kang, Jaeyoung, Lee, Sungjin, Kim, Nam Sung, Kim, Jihong
• Format: Journal Article
• Language: English
• Published: IEEE 01.07.2025
• Subjects: Bandwidth; Compute Express Link; CXL.mem; Data transfer; Decoding; Error correction codes; Flash memories; flash read sequence; NAND flash architecture; NAND flash memory; Optimization; Parallel processing; partial flash read; Sensors; SSD; System-on-chip; Throughput
• ISSN: 1556-6056; 1556-6064
• DOI: 10.1109/LCA.2025.3571321

Emerging data-intensive applications with frequent small random read operations challenge the throughput capabilities of conventional SSD architectures. Although Compute Express Link enabled SSDs allow for fine-grained data access with reduced latency, their read throughput remains limited by legacy block-oriented designs. To address this, we propose <inline-formula><tex-math notation="LaTeX">{\sf srNAND}</tex-math> <mml:math><mml:mi mathvariant="sans-serif">srNAND</mml:mi></mml:math><inline-graphic xlink:href="kim-ieq1-3571321.gif"/> </inline-formula>, an advanced NAND flash architecture for CXL SSDs. It uses a two-stage ECC decoding mechanism to reduce read amplification, an optimized read command sequence to boost parallelism, and a request merging module to eliminate redundant operations. Our evaluation shows that <inline-formula><tex-math notation="LaTeX">{\sf srSSD}</tex-math> <mml:math><mml:mi mathvariant="sans-serif">srSSD</mml:mi></mml:math><inline-graphic xlink:href="kim-ieq2-3571321.gif"/> </inline-formula> can improve read throughput by up to 10.4× compared to conventional CXL SSDs.