Operation model of floating-Si-gate channel-corner-avalanche-transition (FCAT) nonvolatile memory devices
A write/erase model is described for FCAT nonvolatile memory devices which perform write/erase operations with 10–20 V pulses of less than 100-1 μs duration. The amplitude of the threshold voltage shift is analyzed as a function of the source and gate pulse amplitudes using a sample equivalent sourc...
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| Published in | Solid-state electronics Vol. 23; no. 10; pp. 1047 - 1051 |
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| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
Elsevier Ltd
1980
|
| Online Access | Get full text |
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| Summary: | A write/erase model is described for FCAT nonvolatile memory devices which perform write/erase operations with 10–20 V pulses of less than 100-1 μs duration. The amplitude of the threshold voltage shift is analyzed as a function of the source and gate pulse amplitudes using a sample equivalent source circuit. The high level saturated threshold voltage,
V
TH
, obtained by electron injection into the floating gate and the low level saturated threshold voltage,
V
TL
, due to hole injection are shown to be linear functions of
V
G
and
V
S
, and the analysis agrees well with experimental results. The influence of series resistance, including substrate resistance, in the source circuit is also discussed. |
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| ISSN: | 0038-1101 1879-2405 |
| DOI: | 10.1016/0038-1101(80)90183-5 |