Safe and efficient supervised memory systems

• Published in: 2011 IEEE 17th International Symposium on High Performance Computer Architecture pp. 369 - 380
• Main Authors: Bobba, J, Lupon, M, Hill, M D, Wood, D A
• Format: Conference Proceeding Publication
• Language: English
• Published: IEEE 01.02.2011
• Subjects: Arquitectura de computadors; Buffer storage; Data models; Hardware; Informàtica; Load modeling; Multiprocessing systems; Program processors; Proposals; Storage management; Àrees temàtiques de la UPC
• ISBN: 142449432X; 9781424494323
• ISSN: 1530-0897; 2378-203X
• DOI: 10.1109/HPCA.2011.5749744

Supervised Memory systems use out-of-band metabits to control and monitor accesses to normal data memory for such purposes as transactional memory and memory typestate trackers. Previous proposals demonstrate the value of supervised memory systems, but have typically (1) assumed sequential consistency (while most deployed systems use weaker models), and (2) used ad hoc, informal memory specifications (that can be ambiguous and/or incorrect). This paper seeks to make many previous proposals more practical. This paper builds a foundation for future supervised memory systems which (1) operate with the TSO and ×86 memory models, and (2) are formally specified using two supervised memory models. The simpler TSO all model requires all metadata and data accesses to obey TSO, but precludes using store buffers for supervised accesses. The more complex TSO data model relaxes some ordering constraints (allowing store buffer use) but makes programmer reasoning more difficult. To get the benefits of both models, we propose Safe Supervision, which asks programmers to avoid using metabits from one location to order accesses to another. Programmers that obey safe supervision can reason with the simpler semantics of TSO all while obtaining the higher performance of TSO data . Our approach is similar to how data-race-free programs can run on relaxed systems and yet appear sequentially consistent. Finally, we show that TSO data can (a) provide significant performance benefit (up to 22%) over TSO all and (b) can be incorporated correctly and with low overhead into the RTL of an industrial multi-core chip design (OpenSPARC T2).