Probabilistic timing analysis on conventional cache designs

Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., 10 −16 ), resulting in far tighter bounds than conventional analyses. However,...

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Published in2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 603 - 606
Main Authors Kosmidis, Leonidas, Curtsinger, Charlie, Quinones, Eduardo, Abella, Jaume, Berger, Emery, Cazorla, Francisco J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2013
Subjects
Hardware
Layout
Probabilistic logic
Program processors
Runtime
Timing
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Summary:Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., 10 −16 ), resulting in far tighter bounds than conventional analyses. However, the applicability of PTA has been limited because of its dependence on relatively exotic hardware: fully-associative caches using random replacement. This paper extends the applicability of PTA to conventional cache designs via a software-only approach. We show that, by using a combination of compiler techniques and runtime system support to randomise the memory layout of both code and data, conventional caches behave as fully-associative ones with random replacement.
ISBN:1467350710
9781467350716
ISSN:1530-1591
1558-1101
DOI:10.7873/DATE.2013.132