Selective SWIFT-R A Flexible Software-Based Technique for Soft Error Mitigation in Low-Cost Embedded Systems

• Published in: Journal of electronic testing Vol. 29; no. 6; pp. 825 - 838
• Main Authors: Restrepo-Calle, Felipe, Martínez-Álvarez, Antonio, Cuenca-Asensi, Sergio, Jimeno-Morenilla, Antonio
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.12.2013; Springer Nature B.V
• Subjects: CAE) and Design; Circuits and Systems; Computer-Aided Engineering (CAD; Design engineering; Diagnostic tests; Electrical Engineering; Engineering; Fault tolerance; Microprocessors; Performance evaluation; Studies; Spain; Fault tolerance; Embedded systems; Soft errors; COTS electronic components; ); Reliability; Single Event Upset
• ISSN: 0923-8174; 1573-0727
• DOI: 10.1007/s10836-013-5416-6

Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events ( soft errors ), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening , which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best trade-offs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.