Dynamic Flash Memory with fast block refresh feature using double storage gates and one select gate

This paper proposes a Dynamic Flash Memory (DFM) (Sakui and Harada, 2020; 2021 [1,2]) with double storage gates and one select gate based on FinFET and Surrounding Gate Transistor (SGT) (Takato et al., 1988 [3]) architectures. Like DRAM (Dennard, 1967 [4]), refresh is required, but fast block refres...

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Bibliographic Details
Published inMemories - Materials, Devices, Circuits and Systems Vol. 2; p. 100007
Main Authors Sakui, Koji, Harada, Nozomu
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.10.2022
Elsevier
Subjects
Capacitorless DRAM
FinFET
Floating Body
GAA
SOI
Surrounding Gate Transistor (SGT)
Z-RAM
Z-RAM
GAA
FinFET
Surrounding Gate Transistor (SGT)
SOI
Capacitorless DRAM
Floating Body
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Summary:This paper proposes a Dynamic Flash Memory (DFM) (Sakui and Harada, 2020; 2021 [1,2]) with double storage gates and one select gate based on FinFET and Surrounding Gate Transistor (SGT) (Takato et al., 1988 [3]) architectures. Like DRAM (Dennard, 1967 [4]), refresh is required, but fast block refresh improves the duty ratio. Analogous to Flash (Masuoka, 1981 [5]), three basic operations of “0” Erase, “1” Program, and Read are necessary, but the ability to carry out Read-While-Erase (RWE), and Program-While-Erase (PWE) operations in the background results in a faster system.
ISSN:2773-0646
2773-0646
DOI:10.1016/j.memori.2022.100007