An Efficient AES Algorithm for IoT based Applications

• Published in: International journal of engineering and advanced technology Vol. 9; no. 1; pp. 1939 - 1944
• Main Authors: Nandan, V., Rao, R. Gowri Shankar
• Format: Journal Article
• Language: English
• Published: 30.10.2019
• ISSN: 2249-8958; 2249-8958
• DOI: 10.35940/ijeat.A1082.109119

With a massive growth in net communications, there is always a chance of risk to keep the data secret, reliability of data, additionally accessibility of data. An outcome for this is gift cryptographic methodologies which includes the superior Encryption trendy (AES), which might be at gift shield such information, are necessitated to be quick and well protected. In this report, we talk two novel techniques for adapting the foresaid trouble and it is being made potentially through enhancing the design of mix column manipulation of Advance Encryption Standard (AES). An improvement of 1.27 occasions transformed into completed in evaluation to earlier calculations in expressions of pace proficiency [1][2]. As far as hardware structural layout, a space discount of almost thrice change is additionally achieved. AES has input data blocks of 128 bits, with keys length of 128,192 or 256 bits. In this manuscript, a hardware representation of AES algorithm is described using key of length 128 bits. The AES hardware set up is realized using xilinx nexys 4 artix 7 –FPGA board with the help of xilinx ISE design suite. Our work focuses on MAES, a low power AES encryption algorithm which run over the interest [5]. In MAES, a S-Box of one dimension is suggested using new mathematical expression for creating a (n×n) matrix in affine transformation. The percentage efficiency of 18.35% is obtained by MAES than AES, when encrypted packets are transmitted. Thus MAES expends low power compared to that of AES, which is suitable for resource constraint environments.