A 55-64-GHz Low-Power Small-Area LNA in 65-nm CMOS With 3.8-dB Average NF and ~12.8-dB Power Gain

• Published in: IEEE microwave and wireless components letters Vol. 29; no. 2; pp. 128 - 130
• Main Authors: Yaghoobi, Majid, Yavari, Mohammad, Kashani, Milad Haghi, Ghafoorifard, Hassan, Mirabbasi, Shahriar
• Format: Journal Article
• Language: English
• Published: IEEE 01.02.2019
• Subjects: Beamforming; CMOS; Gain; Impedance; Logic gates; low power; low-noise ampli- fier (LNA); millimeter wave (mm wave); Noise measurement; phased-array receivers; Resistors; Topology; Transistors
• ISSN: 1531-1309; 1558-1764
• DOI: 10.1109/LMWC.2018.2890484

This letter presents a low-power small-footprint low-noise amplifier (LNA) that operates over the frequency band of 55-64 GHz. Using a resistor between bulk and substrate (ground) nodes, these two nodes are isolated. This bulk isolation technique is introduced to achieve the maximum gain of the transistor at the desired frequency band. Also, a methodology is proposed to determine the optimal size of transistors to achieve the maximum possible gain. As a proof of concept, the proposed LNA is fabricated in a 65-nm bulk CMOS process, and the design features 12.8 ± 0.5 dB power gain and an average noise figure of 3.8 dB. The output 1-dB compression point of the LNA is −6 dBm. The LNA consumes 8.8 mW from a 1-V supply and excluding the pads occupies a silicon area of 0.23 mm 2 .