TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 39; no. 12; pp. 4482 - 4495
• Main Authors: Zhang, Grace Li, Li, Bing, Li, Meng, Yu, Bei, Pan, David Z., Brunner, Michaela, Sigl, Georg, Schlichtmann, Ulf
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Anti-counterfeiting; Clocks; Counterfeit; Counterfeiting; Delays; embedded security; Gates (circuits); IC camouflage; Logic circuits; Logic gates; netlist camouflage; netlist security; Reverse engineering; wave pipelining
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2020.2974338

With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of authentic chips. This relatively easy counterfeiting is made possible by the use of the standard simple clocking scheme, where all combinational blocks function within one clock period, so that a netlist of combinational logic gates and flip-flops is sufficient to duplicate a design. In this article, we propose to invalidate the assumption that a netlist completely represents the function of a circuit with unconventional timing. With the introduced wave-pipelining (WP) paths, attackers have to capture gate and interconnect delays during reverse engineering, or to test a huge number of combinational paths to identify the WP paths. To hinder the test-based attack, we construct false paths with WP to increase the counterfeiting challenge. The experimental results confirm that WP true paths and false paths can be constructed in benchmark circuits successfully with only a negligible cost, thus thwarting the potential attack techniques.