A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM

• Published in: IEEE journal of solid-state circuits Vol. 55; no. 6; pp. 1665 - 1683
• Main Authors: Zhang, Zhao, Zhu, Guang, Patrick Yue, C.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Charge pumps; CMOS; Digitally controlled capacitor array (DCCA); hybrid dual-path loop; low jitter; low supply voltage; Microprocessors; Phase detectors; Phase locked loops; Phase locked systems; Power consumption; Sampling; sub-sampling charge pump (SSCP); sub-sampling phase detector (SSPD); sub-sampling phase-locked loop (SSPLL); Vibration; Voltage controlled oscillators
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2020.2967562

This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub-sampling CP (SSCP), an integral path SSCP, an LV sub-sampling phase detector, and an LV digitally controlled capacitor array in the LC -based voltage-controlled oscillator, are proposed to simultaneously reduce the PLL integrated jitter and the jitter variation over supply voltage variation. Fabricated in 40-nm CMOS process with a core active area of 0.24 mm 2 , the LVSSPLL operates at 0.65-V supply and achieves 12-16-GHz tuning range, 56.4-fs integrated jitter at 14 GHz, 7.2-mW power consumption, and −256.4-dB figure-of-merit (FoM). The measured integrated jitter variation is less than 14.5 fs within the supply voltage range from 0.62 to 0.7 V, which shows robustness over supply voltage variation.