Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems

This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - and in particular it predicts the contention tasks suffer in the access to mult...

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Bibliographic Details
Published in2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) pp. 1 - 12
Main Authors Trilla, David, Jalle, Javier, Fernandez, Mikel, Abella, Jaume, Cazorla, Francisco J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2016
Subjects
Aerospace electronics
Computational modeling
Microwave integrated circuits
Multicore processing
Program processors
Timing
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Summary:This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - and in particular it predicts the contention tasks suffer in the access to multicore on-chip shared resources. The model presents the key properties of not requiring the application's source code or binary and having high-accuracy and low overhead. The former is of paramount importance in those common scenarios in which several software suppliers work in parallel implementing different applications for a system integrator, subject to different intellectual property (IP) constraints. Our model helps reducing the risk of exceeding the assigned budgets for each application in late design stages and its associated costs.
ISBN:9781467386395
1467386391
DOI:10.1109/RTAS.2016.7461338