Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 40; no. 1; pp. 36 - 43
Main Authors Deleganes, D.J., Barany, M., Geannopoulos, G., Kreitzer, K., Morrise, M., Milliron, D., Singh, A.P., Wijeratne, S.
Format Journal Article
LanguageEnglish
Published IEEE 01.01.2005
Subjects
Adders
Arithmetic
Circuit topology
Clocks
Delay
Frequency
integrated circuit design
Integrated circuit synthesis
Integrated circuit technology
Logic circuits
Microprocessors
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Summary:The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2004.838020