Record RF performance of 45-nm SOI CMOS Technology

• Published in: 2007 IEEE International Electron Devices Meeting pp. 255 - 258
• Main Authors: Sungjae Lee, Jagannathan, B., Narasimha, S., Chou, A., Zamdmer, N., Johnson, J., Williams, R., Wagner, L., Jonghae Kim, Plouchart, J.-O., Pekarik, J., Springer, S., Freeman, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2007
• Subjects: Capacitance measurement; CMOS technology; FETs; Insulation; Leakage current; Length measurement; Parasitic capacitance; Radio frequency; Silicon on insulator technology; Wiring
• ISBN: 1424415071; 9781424415076
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2007.4418916

We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak f T 's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured f T 's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak f T of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.