Employ Present Five Masks Amorphous Silicon Thin-Film Transistor Design and Process Flow to Realize 5-in. InGaZnO Active-Matrix Liquid Crystal Display with Improved Stress Stability
The present five masks bottom gate and staggered amorphous silicon (a-Si) thin-film transistor (TFT) process flow is not suitable for indium--gallium--zinc-oxide (IGZO) TFT because of its vulnerability to post etching process during the source/drain pattern. Bottom gate and coplanar IGZO TFTs were m...
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| Published in | Japanese Journal of Applied Physics Vol. 50; no. 3; pp. 03CB07 - 03CB07-4 |
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| Main Authors | , , , , , |
| Format | Journal Article |
| Language | English |
| Published |
The Japan Society of Applied Physics
01.03.2011
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| Online Access | Get full text |
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| Abstract | The present five masks bottom gate and staggered amorphous silicon (a-Si) thin-film transistor (TFT) process flow is not suitable for indium--gallium--zinc-oxide (IGZO) TFT because of its vulnerability to post etching process during the source/drain pattern. Bottom gate and coplanar IGZO TFTs were made feasible through the reverse of second (channel layer) and third (source/drain electrodes) masks process flow to avoid etching damage problem. Besides, the post IGZO nitrous oxygen (N 2 O) plasma treatment was employed to improve the stress instability. On the basis of secondary ion mass spectrometry (SIMS) and X-ray spectroscopy (XPS) results, it is believed that the post N 2 O plasma treatment passivates the interface states and converts the inhomogeneous and low quality IGZO to the homogeneous and high quality IGZO. In the end, a 5-in. IGZO active-matrix liquid crystal display was demonstrated via five masks bottom gate and coplanar TFT configuration. |
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| AbstractList | The present five masks bottom gate and staggered amorphous silicon (a-Si) thin-film transistor (TFT) process flow is not suitable for indium–gallium–zinc-oxide (IGZO) TFT because of its vulnerability to post etching process during the source/drain pattern. Bottom gate and coplanar IGZO TFTs were made feasible through the reverse of second (channel layer) and third (source/drain electrodes) masks process flow to avoid etching damage problem. Besides, the post IGZO nitrous oxygen (N
2
O) plasma treatment was employed to improve the stress instability. On the basis of secondary ion mass spectrometry (SIMS) and X-ray spectroscopy (XPS) results, it is believed that the post N
2
O plasma treatment passivates the interface states and converts the inhomogeneous and low quality IGZO to the homogeneous and high quality IGZO. In the end, a 5-in. IGZO active-matrix liquid crystal display was demonstrated via five masks bottom gate and coplanar TFT configuration. The present five masks bottom gate and staggered amorphous silicon (a-Si) thin-film transistor (TFT) process flow is not suitable for indium--gallium--zinc-oxide (IGZO) TFT because of its vulnerability to post etching process during the source/drain pattern. Bottom gate and coplanar IGZO TFTs were made feasible through the reverse of second (channel layer) and third (source/drain electrodes) masks process flow to avoid etching damage problem. Besides, the post IGZO nitrous oxygen (N 2 O) plasma treatment was employed to improve the stress instability. On the basis of secondary ion mass spectrometry (SIMS) and X-ray spectroscopy (XPS) results, it is believed that the post N 2 O plasma treatment passivates the interface states and converts the inhomogeneous and low quality IGZO to the homogeneous and high quality IGZO. In the end, a 5-in. IGZO active-matrix liquid crystal display was demonstrated via five masks bottom gate and coplanar TFT configuration. |
| Author | Chang, Jiun-Jye Chen, Po-Lun Hung, Ming-Chin Tu, Chun-Hao Lin, Wei-Ting Hsiao, Hsia-Tsai |
| Author_xml | – sequence: 1 givenname: Ming-Chin surname: Hung fullname: Hung, Ming-Chin organization: AU Optronics, Advanced Display Technology Research Center, No. 1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsinchu 30078, Taiwan, R.O.C – sequence: 2 givenname: Hsia-Tsai surname: Hsiao fullname: Hsiao, Hsia-Tsai organization: AU Optronics, Measurement Technology Department, No. 23, Li-Hsin Rd., Hsinchu Science Park, Hsinchu 30078, Taiwan, R.O.C – sequence: 3 givenname: Wei-Ting surname: Lin fullname: Lin, Wei-Ting organization: AU Optronics, Advanced Display Technology Research Center, No. 1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsinchu 30078, Taiwan, R.O.C – sequence: 4 givenname: Chun-Hao surname: Tu fullname: Tu, Chun-Hao organization: AU Optronics, Advanced Display Technology Research Center, No. 1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsinchu 30078, Taiwan, R.O.C – sequence: 5 givenname: Jiun-Jye surname: Chang fullname: Chang, Jiun-Jye organization: AU Optronics, Advanced Display Technology Research Center, No. 1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsinchu 30078, Taiwan, R.O.C – sequence: 6 givenname: Po-Lun surname: Chen fullname: Chen, Po-Lun organization: AU Optronics, Advanced Display Technology Research Center, No. 1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsinchu 30078, Taiwan, R.O.C |
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| Cites_doi | 10.1063/1.3453870 10.1038/asiamat.2010.5 10.1038/nature03090 10.1063/1.2742790 10.1063/1.2962985 10.1063/1.2927306 10.1149/1.3168522 10.1889/1.3499858 10.1063/1.3232179 |
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| Notes | Bottom gate staggered and coplanar TFT process flow. The fifth mask for the indium tin oxide (ITO) is not included for the simplicity. Transfer curves of six IGZO TFTs ($W/L = 22/5$) on the $320\times 400$ mm 2 glass substrate. The evolution of transfer curves under (a) PBTS or (b) NBTS. The insets show the $V_{\text{th}}$ shifts for a-Si and IGZO TFTs under the same stress condition after 2000 s. The evolution of $V_{\text{th}}$ shifts for PBTS and NBTS of a-Si TFTs and IGZO TFTs with (a) SiO x or (b) SiN x as the gate dielectric material. The insets show the $V_{\text{th}}$ shifts for a-Si and IGZO TFTs under the same stress condition after 2000 s. The evolution of transfer curves for IGZO TFTs with N 2 O plasma treatment under (a) PBTS or (b) NBTS condition. The evolution of $V_{\text{th}}$ shifts for PBTS and NBTS of a-Si TFTs and IGZO TFTs after N 2 O plasma treatment with (a) SiO x or (b) SiN x as the gate dielectric material. The insets show the $V_{\text{th}}$ shifts for a-Si and IGZO TFTs under the same stress condition after 2000 s. (a) XPS depth profile of normal IGZO and N 2 O plasma treated IGZO (b) SIMS depth profile of In 2 O 3 within IGZO (c) SIMS depth profile of Ga 2 O 3 within IGZO (d) SIMS depth profile of ZnO within IGZO. The image of 5-in. IGZO AM-LCD panel. |
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| Snippet | The present five masks bottom gate and staggered amorphous silicon (a-Si) thin-film transistor (TFT) process flow is not suitable for... The present five masks bottom gate and staggered amorphous silicon (a-Si) thin-film transistor (TFT) process flow is not suitable for indium–gallium–zinc-oxide... |
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| Title | Employ Present Five Masks Amorphous Silicon Thin-Film Transistor Design and Process Flow to Realize 5-in. InGaZnO Active-Matrix Liquid Crystal Display with Improved Stress Stability |
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