A stackable cross point Phase Change Memory

• Published in: 2009 IEEE International Electron Devices Meeting (IEDM) pp. 1 - 4
• Main Authors: DerChang Kau, Tang, S., Karpov, I.V., Dodge, R., Klehn, B., Kalb, J.A., Strand, J., Diaz, A., Leung, N., Wu, J., Lee, S., Langtry, T., Kuo-wei Chang, Papagianni, C., Jinwook Lee, Hirst, J., Erra, S., Flores, E., Righos, N., Castro, H., Spadini, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2009
• Subjects: CMOS logic circuits; CMOS memory circuits; Decoding; Dynamic range; Logic arrays; Logic functions; Nonvolatile memory; Phase change materials; Phase change memory; Switches
• ISBN: 9781424456390; 1424456398
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2009.5424263

A novel scalable and stackable nonvolatile memory technology suitable for building fast and dense memory devices is discussed. The memory cell is built by layering a storage element and a selector. The storage element is a Phase Change Memory (PCM) cell and the selector is an Ovonic Threshold Switch (OTS). The vertically integrated memory cell of one PCM and one OTS (PCMS) is embedded in a true cross point array. Arrays are stacked on top of CMOS circuits for decoding, sensing and logic functions. A RESET speed of 9 nsec and endurance of 10 6 cycles are achieved. One volt of dynamic range delineating SET vs. RESET is also demonstrated.