Hardware Design and Evaluation of an FPGA-Based Network Switch Supporting Asynchronous Traffic Shaping for Time Sensitive Networking

• Published in: IEEE access Vol. 12; pp. 123149 - 123165
• Main Authors: Ben Ahmed, Akram, Hirofuchi, Takahiro, Fukai, Takaaki
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Asynchronous communication; Asynchronous traffic shaping; Bridges; Computer architecture; Ethernet; Field programmable gate arrays; FPGA; Hardware; Network latency; Quality of service; Reconfigurable hardware; Sensitivity analysis; Streams; Surveys; switch architecture; Switches; Telecommunication traffic; Time measurement; time sensitive networks
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3451448

Time Sensitive Networking (TSN) has been widely adopted to respond to the growing need for reliable and latency-bound communication in 5G/Post5G applications. It introduces a set of new open standards to conventional IEEE 802.3 Ethernet networks that aim to provide deterministic, reliable, high-bandwidth, and low-latency communication. Although many TSN-compliant switches have been proposed in the industry, only a few academic research works have proposed a comprehensive, reconfigurable, and open-source hardware switch architecture supporting deterministic transmission in data networks. In this paper, we present a reconfigurable hardware architecture of an FPGA-based network switch supporting TSN. The proposed switch leverages Asynchronous Traffic Shaping (ATS) as its traffic shaping algorithm to forward frames in a per-flow interleaved transmission. We present the key architectural components and implementation aspects of the proposed switch and discuss the evaluation results in a fair amount of detail to validate our proposal.