3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture

The Gate-Induce-Drain-Leakage (GIDL)-assisted body biasing for erase, which is a technique essential to enabling 3DNAND Flash CMOS Under Array architectures, has been extensively studied and successfully optimized to achieve high-performance, reliable erase operation. This paper reviews the main fea...

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Bibliographic Details
Published in2017 IEEE International Memory Workshop (IMW) pp. 1 - 4
Main Authors Caillat, C., Beaman, K., Bicksler, A., Camozzi, E., Ghilardi, T., Huang, G., Liu, H., Liu, Y., Mao, D., Mujumdar, S., Righetti, N., Ulrich, M., Venkatasubramanian, C., Yang, X., Goda, A., Gowda, S., Mebrahtu, H., Sanda, H., Yuwen, Y., Koval, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2017
Subjects
Computer architecture
Electric potential
Junctions
Logic gates
Performance evaluation
Reliability
Transient analysis
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Summary:The Gate-Induce-Drain-Leakage (GIDL)-assisted body biasing for erase, which is a technique essential to enabling 3DNAND Flash CMOS Under Array architectures, has been extensively studied and successfully optimized to achieve high-performance, reliable erase operation. This paper reviews the main features of GIDL-assisted body biasing and GIDL optimization methods ensuring the best erase effectiveness and variability control. Finally, the excellent reliability of the selector gate devices over Program/Erase cycles is demonstrated, proving the reliability of this technique.
DOI:10.1109/IMW.2017.7939067