A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability

Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive 3D TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (~20 nm) and poly channel thickness (~10nm) can not be scaled furth...

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Bibliographic Details
Published in2010 IEEE International Memory Workshop pp. 1 - 4
Main Authors Yi-Hsuan Hsiao, Hang-Ting Lue, Tzu-Hsuan Hsu, Kuang-Yeu Hsieh, Chih-Yuan Lu
Format Conference Proceeding
LanguageEnglish
Published IEEE 2010
Subjects
Costs
Lithography
Memory architecture
Scalability
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Summary:Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive 3D TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (~20 nm) and poly channel thickness (~10nm) can not be scaled further. Among them VG may have the best X-direction scalability to F~2X nm node, and no penalty of increasing Z layer number since the channel current flows horizontally. We propose a buried-channel junction-free NAND to improve the read current for all 3D NAND arrays and our simulation results well support this structure. For the first time, "Z-interference" in 3D NAND Flash is examined and it indicates a new Z-direction scaling limitation. The present work is of crucial importance in understanding various 3D NAND Flash approaches.
ISBN:9781424467198
1424467195
ISSN:2159-483X
DOI:10.1109/IMW.2010.5488390