Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

• Published in: IEEE transactions on electron devices Vol. 53; no. 5; pp. 1096 - 1106
• Main Authors: Fei Li, Mudanai, S.P., Yang-Yu Fan, Register, L.F., Banerjee, S.K.
• Format: Journal Article
• Language: English
• Published: IEEE 01.05.2006
• Subjects: Direct tunneling; Fowler-Nordheim (F-N) tunneling; Franz two-band model; Hafnium compounds; high; Leakage currents; MIS devices; MOS devices; quantum-mechanical effects; Semiconductor device modeling; Silicon compounds; Tunneling; Wentzel-Kramers-Brillouin (WKB) theory
• ISSN: 0018-9383
• DOI: 10.1109/TED.2006.871877

Building on a previously presented compact gate capacitance (C/sub g/-V/sub g/) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I/sub g/-V/sub g/) is provided for both ultrathin SiO/sub 2/ and high-dielectric constant (high-/spl kappa/) gate stacks of equivalent oxide thickness (EOT) down to /spl sim/ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C/sub g/-V/sub g/ model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schro/spl uml/dinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO/sub 2/ and high-/spl kappa//SiO/sub 2/ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO/sub 2/, Si/sub 3/N/sub 4/, and high-/spl kappa/ (e.g., HfO/sub 2/) gate stacks on (100) Si with EOTs down to /spl sim/ 1-nm show excellent agreement.