Design of a low power and robust VLSI power line interference canceler with optimized arithmetic operators

• Published in: Analog integrated circuits and signal processing Vol. 112; no. 2; pp. 247 - 261
• Main Authors: da Rosa, Morgana Macedo Azevedo, da Costa, Patrícia Ücker, da Costa, Eduardo Antonio César, Almeida, Sérgio J. M., Paim, Guilherme, Bampi, Sergio
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.08.2022; Springer Nature B.V
• Subjects: Adaptive filters; Architecture; Arithmetic; Circuits and Systems; Electric filters; Electric generators; Electrical Engineering; Electrocardiography; Electroencephalography; Energy dissipation; Engineering; Hardware; Harmonic distortion; Harmonic generators; Integrated circuits; Interference; Power lines; Robustness; Signal,Image and Speech Processing; Harmonics generation; Low power architectures; VLSI design; Interference canceling; LMS adaptive filter
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-022-02050-x

The electric generator’s functional performance suffers from harmonic distortions such as first, second, and third-order. This work proposes a low power dissipation VLSI hardware architecture for a robust power line interference canceling (PLIC) in biopotential signals. Our proposed Least Mean Square (LMS) architecture presents just four clock cycles of latency per sample. The Harmonic Generator (HG) architectures are exploited and optimized in their arithmetic operations. We substituted conventional multipliers with adders and shifters and used efficient and previously published squarer units. In particular, the combination of radix-4 squarer unit and 3–2 subtractor compressor architecture is an efficient alternative for use in the HG. Our VLSI synthesis results show that combining the optimized adaptive filters LMS and HG’s hardware architecture, the proposed approach turns the PLIC VLSI structure robust and power-efficient. It effectively suppresses interferences in ECG (Electrocardiogram), EEG (Electroencephalogram), EMG (Electromyogram), and EOG (Electrooculogram) signals. Notably, the PLIC architecture is more efficient in the circuit area and power dissipation with the radix-4 and 3–2 subtractor compressor in the HG, saving up to 4.98 times in total power and 30.46% in the VLSI area, compared to the state-of-the-art solution.