Improve performance of the digital sinusoidal generator in FPGA by memory usage optimization

This paper presented the improvement in the performance of the digital sinusoidal signal generator, which was implemented in FPGA, by optimizing the usage of the available memory onboard. The sine wave was generated by using a Lookup Table method, where its pre-calculated values were stored in the o...

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Published inInternational journal of electrical and computer engineering (Malacca, Malacca) Vol. 9; no. 3; p. 1742
Main Authors Jidin, Aiman Zakwan, Mahzan, Irna Nadira, A. Subki, A. Shamsul Rahimi, Wan Hassan, Wan Haszerila
Format Journal Article
LanguageEnglish
Published Yogyakarta IAES Institute of Advanced Engineering and Science 01.06.2019
Subjects
Computer simulation
Cyclones
Frequency ranges
Lookup tables
Optimization
Performance enhancement
Signal generators
Sine waves
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Summary:This paper presented the improvement in the performance of the digital sinusoidal signal generator, which was implemented in FPGA, by optimizing the usage of the available memory onboard. The sine wave was generated by using a Lookup Table method, where its pre-calculated values were stored in the onboard memory, and its frequency can be adjustable by changing the incremental step value of the memory address. In this proposed research, the memory stores only 25000 samples of the first quarter from a period of a sine wave and thus, the output signal accuracy was increased and the output frequency range was expanded, compared to the previous research. The proposed design was successfully developed and implemented in ALTERA Cyclone III DE0 FPGA Development Board, and its functionality was validated via functional simulation in Modelsim and also hardware experimental results observation in SignalTap II.
ISSN:2088-8708
2088-8708
DOI:10.11591/ijece.v9i3.pp1742-1749