DC and Analog/RF Performance Evaluation Using Dual Metal Gate Work Function Engineering of Junctionless Cylindrical Gate All Around Si Nanowire MOSFET Using NEGF Approach for Upcoming Sub 5 nm Technology Node

• Published in: International journal of precision engineering and manufacturing Vol. 25; no. 9; pp. 1885 - 1897
• Main Authors: Sanjay, Kumar, Vibhor, Vohra, Anil
• Format: Journal Article
• Language: English
• Published: Seoul Korean Society for Precision Engineering 01.09.2024; Springer Nature B.V
• Subjects: Comparative studies; Devices; Engineering; Green's functions; Industrial and Production Engineering; Ion currents; Materials Science; MOSFETs; Nanowires; Performance evaluation; Poisson equation; Regular Paper; Silicon dioxide; Technology assessment; Threshold voltage; Transconductance; Transit time; Work functions; SiNW; JL; NEGF; DM CGAA; IM
• ISSN: 2234-7593; 2005-4602
• DOI: 10.1007/s12541-024-01023-6

Present work investigates the DC and Analog/RF characteristics such as the drain current ( I D ), Transconductance ( g m ) , Transconductance Generation Factor (TGF), Cut-off frequency ( f T ) , Frequency Transconductance Product (FTP), Transit time ( τ ) , and the total resistance of the source region, drain region, and channel resistance ( R S D + C H ) for Dual Metal (DM) Inversion Mode (IM) and Junctionless (JL) Cylindrical Gate All Around (CGAA) Silicon nanowire (SiNW) MOSFETs with 5 nm gate length using Silvaco ATLAS 3D TCAD. In this work, the Non-Equilibrium Green’s Function approach along with the self-consistent solution of Schrödinger’s equation and Poisson’s equation has been considered. The channel is taken to be lightly doped in the case of IM DM CGAA SiNW type of device. The effect of DM Gate work function engineering for SiNW channel of diameter 3 nm with gate oxide ( SiO 2 ) the thickness of 0.8 nm on I D , g m , TGF, f T , τ , FTP and R CH has been studied. Moreover, a comparative study has been made between IMDM and JLDM CGAA SiNW devices with the above-mentioned parameters. For the JL device, the optimization of doping concentration is performed to get the same (i) I ON current and (ii) threshold voltage (V TH ) as the IM device. About 3.09 times and 21.89 times reduction in I OFF is seen for the same I ON and V TH optimized devices respectively as compared to IM device. It has been found that DM Gate variation minimizes drain-induced barrier lowering (DIBL) in IM and JL devices. The JL SiNW showed much lower DIBL ~ 16.46 mV/V, a near ideal SS ~ 60 mV/dec, and higher I ON / I OFF current ratio ~ 7.04 × 10 8 which is much better as compared to those reported in the literature for cylindrical gate all around (CGAA) devices. Also, it is found that the JL SiNW device performs better than IM in terms of SS, DIBL, I ON / I OFF , g m , TGF, f T , τ , FTP and R S D + C H .