Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction

• Published in: Artificial life and robotics Vol. 27; no. 3; pp. 541 - 546
• Main Authors: Shinyamada, Kohei, Yamawaki, Akira
• Format: Journal Article
• Language: English
• Published: Tokyo Springer Japan 01.08.2022; Springer Nature B.V
• Subjects: Artificial Intelligence; Cameras; Computation by Abstract Devices; Computer Science; Control; Embedded systems; Hardware description languages; High level languages; High level synthesis; Image processing; Mechatronics; Original Article; Power consumption; Power management; Robotics; Software; Subtraction; Real camera system; High-level synthesis; Image processing; FPGA; HLS
• ISSN: 1433-5298; 1614-7456
• DOI: 10.1007/s10015-022-00777-4

Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was N = 4 , which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing.