A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals
A low-power three-dimensional (3-D) rendering engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be realized with the help of low-power pipeline structure,...
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Published in | IEEE journal of solid-state circuits Vol. 39; no. 7; pp. 1101 - 1109 |
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Main Authors | , , , , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.07.2004
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | A low-power three-dimensional (3-D) rendering engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be realized with the help of low-power pipeline structure, optimization of datapath, extensive clock gating, texture address alignment, and the distributed activation of embedded DRAM. The scalable performance reaches up to 100 Mpixels/s and 400 Mtexels/s at 50 MHz. The chip is implemented with 0.16-/spl mu/m pure DRAM process to reduce the fabrication cost of the embedded-DRAM chip. The logic with DRAM takes 46 mm/sup 2/ and consumes 140 mW at 33-MHz operation, respectively. The 3-D graphics images are successfully demonstrated by using the fabricated chip on the prototype PDA board. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2004.829406 |