A Second-Order Purely VCO-Based CT \Delta\Sigma ADC Using a Modified DPLL Structure in 40-nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 55; no. 2; pp. 356 - 368
• Main Authors: Zhong, Yi, Li, Shaolan, Tang, Xiyuan, Shen, Linxiao, Zhao, Wenda, Wu, Siliang, Sun, Nan
• Format: Journal Article
• Language: English
• Published: IEEE 01.02.2020
• Subjects: Analog-to-digital converter (ADC); Calibration; Clocks; data-weighted averaging (DWA); digital phase-locked loop (DPLL); digital-to-analog converter (DAC); Phase frequency detector; Phase locked loops; switched-ring oscillator (SRO); Switches; time-domain signal processing; time-to-digital converter (TDC); voltage-controlled oscillator (VCO)-based ΔΣ ADC; Voltage-controlled oscillators; ΔΣ ADC
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2019.2948008

This article presents a power-efficient purely voltage-controlled oscillator (VCO)-based second-order continuous-time (CT) ΔΣ analog-to-digital converter (ADC), featuring a modified digital phase-locked loop (DPLL) structure. The proposed ADC combines a VCO with a switched-ring oscillator (SRO)-based time-to-digital converter (TDC), which enables second-order noise shaping without any operational transconductance amplifiers (OTAs). The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. An array of phase/frequency detectors (PFDs) is used to relax the requirement on the VCO center frequency and thus reduces the VCO power and noise. The proposed architecture also realizes an intrinsic tri-level data-weighted averaging (DWA). A prototype chip is fabricated in a 40-nm CMOS process. The proposed ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 69.4 dB over 5.2-MHz bandwidth, while operating at the 260 MS/s and consuming 0.86 mW from a 1.1-V supply.