FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm

• Published in: International journal of reconfigurable and embedded systems Vol. 12; no. 2; p. 157
• Main Authors: Ramalingam, Nithya, Thiagarajan, Anitha
• Format: Journal Article
• Language: English
• Published: Yogyakarta IAES Institute of Advanced Engineering and Science 01.07.2023
• Subjects: Algorithms; Circuits; Decision trees; Field programmable gate arrays; Hardware description languages; Inverters; Machine learning; Pulse duration modulation; Real time; Switches; VHSIC (circuits)
• ISSN: 2089-4864; 2722-2608; 2089-4864
• DOI: 10.11591/ijres.v12.i2.pp157-164

The proposed method involves the fault analysis of the inverter switches present in the multi-level inverter (MLI) circuitry. The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. The multi-level inverter utilized in this work is a 7-level switched ladder multi-level inverter. There is 4 number of switches in the design of a 7-level inverter driven by the non-carrier digital pulse width modulation signals. The non-carried-based digital pulse-width modulator (DPWM) generation is generated using the event angle for the 7-level of the switched ladder inverter. The proposed method investigates the stuck-at-fault occurrences of the 4 switches in the inverter by manipulating the decision tree parameters such as entropy, information gain, and decision tree. Based on the decision tree, the very high-speed integrated circuit hardware description language (VHDL) code is developed by making use of the behavioral modeling and validated for the power, area in the Xilinx Vivado tool. The real-time feasibility is verified for the proposed method by synthesizing the developed VHDL code in the field programmable gate array (FPGA) device.