FPGA based area-power-performance analysis of LMS filter using conventional and proposed multipliers

Abstract This paper compares LMS filter-based adaptive channel equalizer, implemented on Vertex 7 FPGA using several existing and proposed multipliers. The three main performance parameters taken into consideration are the consumed resources (in terms of lookup tables), utilized power (among various...

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Published inJournal of physics. Conference series Vol. 1860; no. 1; p. 12010
Main Authors Pathan, A, Memon, T D, Sohu, F Khan
Format Journal Article
LanguageEnglish
Published Bristol IOP Publishing 01.03.2021
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Abstract Abstract This paper compares LMS filter-based adaptive channel equalizer, implemented on Vertex 7 FPGA using several existing and proposed multipliers. The three main performance parameters taken into consideration are the consumed resources (in terms of lookup tables), utilized power (among various design components), and the performance achieved (in terms of observed frequency). The results show the area-power-performance tradeoff amongst the conventional and proposed multipliers based designs. It is to mention that the proposed multipliers result in more compact systems due to less utilization of resources in all means.
AbstractList This paper compares LMS filter-based adaptive channel equalizer, implemented on Vertex 7 FPGA using several existing and proposed multipliers. The three main performance parameters taken into consideration are the consumed resources (in terms of lookup tables), utilized power (among various design components), and the performance achieved (in terms of observed frequency). The results show the area-power-performance tradeoff amongst the conventional and proposed multipliers based designs. It is to mention that the proposed multipliers result in more compact systems due to less utilization of resources in all means.
Abstract This paper compares LMS filter-based adaptive channel equalizer, implemented on Vertex 7 FPGA using several existing and proposed multipliers. The three main performance parameters taken into consideration are the consumed resources (in terms of lookup tables), utilized power (among various design components), and the performance achieved (in terms of observed frequency). The results show the area-power-performance tradeoff amongst the conventional and proposed multipliers based designs. It is to mention that the proposed multipliers result in more compact systems due to less utilization of resources in all means.
Author Pathan, A
Sohu, F Khan
Memon, T D
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Cites_doi 10.7158/E11-061.2013.10.1
10.1109/82.199898
10.1145/1240233.1240234
10.1007/s11265-012-0664-8
10.1093/qjmam/4.2.236
10.1109/TCSI.2006.885976
10.1049/ip-cdt:20045086
10.1109/TSP.2007.914926
10.1109/4.509848
10.3182/20120523-3-CZ-3015.00048
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References Flateau (JPCS_1860_1_012010bib18) 2014
Zhuo (JPCS_1860_1_012010bib21) 2005
Dadda (JPCS_1860_1_012010bib9) 1965; 34
Memon (JPCS_1860_1_012010bib6) 2013; 10
Memon (JPCS_1860_1_012010bib12) 2018
Wallace (JPCS_1860_1_012010bib8) 1964
Todman (JPCS_1860_1_012010bib20) 2005; 152
Shanthala (JPCS_1860_1_012010bib4) 2009; 31
Meyr (JPCS_1860_1_012010bib16) 1997
Hawley (JPCS_1860_1_012010bib3) 1996; 31
Pathan (JPCS_1860_1_012010bib13) 2017
Guo (JPCS_1860_1_012010bib19) 1992; 39
Voronenko (JPCS_1860_1_012010bib14) 2007; 3
Rais (JPCS_1860_1_012010bib11) 2009; 5
de Dinechin (JPCS_1860_1_012010bib15) 2019
Meher (JPCS_1860_1_012010bib2) 2008; 56
Booth (JPCS_1860_1_012010bib7) 1951; 4
Maharaja (JPCS_1860_1_012010bib10) 2009
Milik (JPCS_1860_1_012010bib17) 2012; 45
Cheng (JPCS_1860_1_012010bib1) 2007; 54
Memon (JPCS_1860_1_012010bib5) 2013; 70
References_xml – volume: 31
  start-page: 19
  year: 2009
  ident: JPCS_1860_1_012010bib4
  article-title: High speed and low power FPGA implementation of FIR filter for DSP applications
  publication-title: European Journal of Scientific Research
  contributor:
    fullname: Shanthala
– start-page: 276
  year: 2018
  ident: JPCS_1860_1_012010bib12
  article-title: An approach to LUT based multiplier for short word length DSP systems
  contributor:
    fullname: Memon
– year: 1997
  ident: JPCS_1860_1_012010bib16
  contributor:
    fullname: Meyr
– volume: 10
  start-page: 107
  year: 2013
  ident: JPCS_1860_1_012010bib6
  article-title: The impact of alternative encoding techniques on field programmable gate array implementation of sigma-delta modulated ternary finite impulse response filters
  publication-title: Australian Journal of Electrical and Electronics Engineering
  doi: 10.7158/E11-061.2013.10.1
  contributor:
    fullname: Memon
– volume: 39
  start-page: 723
  year: 1992
  ident: JPCS_1860_1_012010bib19
  article-title: The efficient memory-based VLSI array designs for DFT and DCT
  publication-title: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
  doi: 10.1109/82.199898
  contributor:
    fullname: Guo
– year: 2014
  ident: JPCS_1860_1_012010bib18
  contributor:
    fullname: Flateau
– start-page: 63
  year: 2005
  ident: JPCS_1860_1_012010bib21
  contributor:
    fullname: Zhuo
– volume: 3
  start-page: 11
  year: 2007
  ident: JPCS_1860_1_012010bib14
  article-title: Multiplierless multiple constant multiplication
  publication-title: ACM Transactions on Algorithms (TALG)
  doi: 10.1145/1240233.1240234
  contributor:
    fullname: Voronenko
– volume: 70
  start-page: 275
  year: 2013
  ident: JPCS_1860_1_012010bib5
  article-title: Power-area-performance characteristics of FPGA-based sigma-delta fir filters
  publication-title: Journal of Signal Processing Systems
  doi: 10.1007/s11265-012-0664-8
  contributor:
    fullname: Memon
– volume: 4
  start-page: 236
  year: 1951
  ident: JPCS_1860_1_012010bib7
  article-title: A signed binary multiplication technique
  publication-title: The Quarterly Journal of Mechanics and Applied Mathematics
  doi: 10.1093/qjmam/4.2.236
  contributor:
    fullname: Booth
– start-page: 346
  year: 2017
  ident: JPCS_1860_1_012010bib13
  contributor:
    fullname: Pathan
– start-page: 14
  year: 1964
  ident: JPCS_1860_1_012010bib8
  article-title: A suggestion for a fast multiplier
  contributor:
    fullname: Wallace
– volume: 5
  start-page: 124
  year: 2009
  ident: JPCS_1860_1_012010bib11
  article-title: Efficient hardware realization of truncated multipliers using FPGA
  publication-title: International Journal of Engineering and Applied Sciences
  contributor:
    fullname: Rais
– volume: 54
  start-page: 280
  year: 2007
  ident: JPCS_1860_1_012010bib1
  article-title: Low-cost parallel FIR filter structures with 2-stage parallelism
  publication-title: IEEE Transactions on Circuits and Systems I: Regular Papers
  doi: 10.1109/TCSI.2006.885976
  contributor:
    fullname: Cheng
– volume: 152
  start-page: 193
  year: 2005
  ident: JPCS_1860_1_012010bib20
  article-title: Reconfigurable computing: architectures and design methods
  publication-title: IEE Proceedings-Computers and Digital Techniques
  doi: 10.1049/ip-cdt:20045086
  contributor:
    fullname: Todman
– volume: 56
  start-page: 3009
  year: 2008
  ident: JPCS_1860_1_012010bib2
  article-title: FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic
  publication-title: IEEE transactions on signal processing
  doi: 10.1109/TSP.2007.914926
  contributor:
    fullname: Meher
– start-page: 151
  year: 2019
  ident: JPCS_1860_1_012010bib15
  contributor:
    fullname: de Dinechin
– volume: 31
  start-page: 656
  year: 1996
  ident: JPCS_1860_1_012010bib3
  article-title: Design techniques for silicon compiler implementations of high-speed FIR digital filters
  publication-title: IEEE Journal of Solid-State Circuits
  doi: 10.1109/4.509848
  contributor:
    fullname: Hawley
– volume: 45
  start-page: 249
  year: 2012
  ident: JPCS_1860_1_012010bib17
  article-title: On Mapping of DSP48 Units for Arithmetic Operation in Reconfigurable Logic Controllers
  publication-title: IFAC Proceedings Volumes
  doi: 10.3182/20120523-3-CZ-3015.00048
  contributor:
    fullname: Milik
– start-page: 5
  year: 2009
  ident: JPCS_1860_1_012010bib10
  contributor:
    fullname: Maharaja
– volume: 34
  start-page: 349
  year: 1965
  ident: JPCS_1860_1_012010bib9
  article-title: Some schemes for parallel multipliers
  publication-title: Alta frequenza
  contributor:
    fullname: Dadda
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Snippet Abstract This paper compares LMS filter-based adaptive channel equalizer, implemented on Vertex 7 FPGA using several existing and proposed multipliers. The...
This paper compares LMS filter-based adaptive channel equalizer, implemented on Vertex 7 FPGA using several existing and proposed multipliers. The three main...
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StartPage 12010
SubjectTerms Adaptive filters
Lookup tables
Multipliers
Physics
Power consumption
Title FPGA based area-power-performance analysis of LMS filter using conventional and proposed multipliers
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