A 4.5-to-14 GHz PLL-based Clock Driver with Wide-range 3-shaped LC-VCOs for GDDR6 DRAM Test

• Published in: Journal of semiconductor technology and science Vol. 24; no. 3; pp. 284 - 288
• Main Authors: Kye, Chan-Ho, Kim, Jihee, Jeong, Deog-Kyoon, Choo, Min-Seong
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.06.2024
• Subjects: 전기공학; DRAM test; LCVCO; CML driver; phase-locked loop (PLL); built-out tester (BOT)
• ISSN: 1598-1657; 2233-4866; 2233-4866; 1598-1657
• DOI: 10.5573/JSTS.2024.24.3.284

This letter presents a 4.5-to-14 GHz phase-locked loop (PLL)-based clock driver with wide-range 3-shaped LC-VCOs for GDDR6 DRAM test. We use two frequency modes to generate a write clock (WCK) from DC-to-14 GHz. In low-frequency mode under 4.5 GHz, the input from the automatic test equipment (ATE) is bypassed to WCK output. In high-frequency mode, PLL supports high-frequency WCK with good phase noise employing LC-VCOs. We propose 3 LC-VCOs to cover 48 frequency bands which support a frequency range from 4.5-to-14 GHz. Moreover, the current-mode driver with output common mode level control is proposed to provide programmability of the received clock input crossing point for the GDDR6 DRAM test. The prototype chip was fabricated in a 40 nm CMOS technology. The measured frequency tuning range is from 4.5-to-14 GHz with a tuning ratio of 102.7 %. The measured output common mode peak-to-peak difference is 200 mV. The measured integrated RMS jitter is 129 fsrms at 7 GHz, 180 fsrms at 11 GHz, and 365 fsrms at 14 GHz, respectively. KCI Citation Count: 0