High-PSRR Low-dropout Regulator with Fast Transient Response Time and Low Output Peak Voltage

This study proposes the feed-forward ripple cancellation (FFRC) technique to low drop-out (LDO) regulator. By adding load tracking impedance to the gate of pass transistor, it is possible to secure stability with a 100-nF capacitor having low ESR and be obtained less than 35 ns response time. In all...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 21; no. 4; pp. 292 - 296
Main Authors Kim, Nahyun, Song, Junyoung
Format Journal Article
LanguageEnglish
Published 대한전자공학회 01.08.2021
Subjects
전기공학
fast transient response time
Low-dropout (LDO) regulator
low output peak voltage
power-supply rejection ratio (PSRR)
Online AccessGet full text
ISSN1598-1657
2233-4866
DOI10.5573/JSTS.2021.21.4.292

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Summary:This study proposes the feed-forward ripple cancellation (FFRC) technique to low drop-out (LDO) regulator. By adding load tracking impedance to the gate of pass transistor, it is possible to secure stability with a 100-nF capacitor having low ESR and be obtained less than 35 ns response time. In all frequency bands, a power supply rejection ratio (PSRR) less than -70 dB is obtained when the load current is 10 mA. The circuit is implemented in 65-nm CMOS process. KCI Citation Count: 0
ISSN:1598-1657
2233-4866
DOI:10.5573/JSTS.2021.21.4.292