Design and Development of Novel Refresh Technique for Gain Cell Embedded DRAM

• Published in: SN computer science Vol. 4; no. 6; p. 786
• Main Authors: Shravan, Chintam, Fatima, Kaleem, Sekhar, P. Chandra
• Format: Journal Article
• Language: English
• Published: Singapore Springer Nature Singapore 01.11.2023; Springer Nature B.V
• Subjects: Advances in Computational Approaches for Image Processing; Application specific integrated circuits; Capacitors; Cloud Applications and Network Security; Computer Imaging; Computer Science; Computer Systems Organization and Communication Networks; Data integrity; Data loss; Data Structures and Information Theory; Digital signal processors; Dynamic random access memory; Embedded systems; Energy consumption; High performance computing; Information Systems and Communication Service; Memory management; Microprocessors; Original Research; Pattern Recognition and Graphics; Power consumption; Power management; Pseudorandom; Random access memory; Software Engineering/Programming and Operating Systems; Static random access memory; Vision; Wireless Networks; GC-eDRAM; Zynq SoC; AXI; Refresh operation; Memory controller; Parallel read and write
• ISSN: 2661-8907; 2662-995X; 2661-8907
• DOI: 10.1007/s42979-023-02223-z

Gain cell embedded DRAM (GC-eDRAM) is a type of dynamic random access memory (DRAM) architecture that is widely used in embedded systems, such as microcontrollers, digital signal processors, and application-specific integrated circuits. In GC-eDRAM, the refresh operation is necessary to prevent data loss due to charge leakage from the memory cells. Unlike SRAM, DRAM stores data as a charge in a capacitor, and this charge slowly leaks away over time, causing data loss if not periodically refreshed. The refresh operation in GC-eDRAM involves scanning through the memory array and reading each cell's contents before writing it back, thus restoring the charge to the capacitor. This process can be performed in several ways, such as row-by-row, column-by-column, or by using a pseudo-random pattern to minimize the impact on system performance. The conventional memory refresh operations are not up to the mark to provide the better performance in terms of speed of the refresh rate and power consumption. This work proposes a novel Advance eXtensible Interface (AXI)-based memory read and write operations in memory controller. The proposed method executes the read and write operations in parallel mode which can reduce the latency in the refresh operation. The proposed method is developed by using Verolg HDL language and Xilinx Vivado tool. The results are compared with sequential mode of operation and existing method. In both cases, the proposed method exhibits the better performance. By using the proposed method, the 40% clock pulses and 50% of the power is reduced.