INVITED: A 0.26% BER, Machine-Learning Resistant 1028 Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection
A 10 28 challenge-response strong-PUF circuit is fabricated in 14nm CMOS, demonstrating modeling attack resistance across 6-million training samples. Two-stage nonlinearly cascaded PUF array organization with adversarial challenge selection increases modeling complexity by 4×, limiting ML attack acc...
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Published in | 2020 57th ACM/IEEE Design Automation Conference (DAC) pp. 1 - 3 |
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Main Authors | , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.07.2020
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Subjects | |
Online Access | Get full text |
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Summary: | A 10 28 challenge-response strong-PUF circuit is fabricated in 14nm CMOS, demonstrating modeling attack resistance across 6-million training samples. Two-stage nonlinearly cascaded PUF array organization with adversarial challenge selection increases modeling complexity by 4×, limiting ML attack accuracy to ~50%. A configurable cross-coupled inverter-based entropy source with stability-aware challenge pruning enables 9.8× higher array density, linearly-scaling enrollment data and worst-case bit-error-rate of 0.26% measured across 650-850mV, 0-100°C operation. |
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DOI: | 10.1109/DAC18072.2020.9218720 |