A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drain

A novel CMOS process architecture comprising of 1.5 nm equivalent oxide thickness (EOT) oxide/nitride (O/N) gate dielectric, self aligned shallow trench isolation (SASTI), dual poly/W gate and W cladded source/drain is shown to have low gate dielectric leakage with excellent boron blocking, no dopan...

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Bibliographic Details
Published inIEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 pp. 669 - 672
Main Authors Blosse, A., Ramkumar, K., Gopalan, P., Hsu, C.T., Narayanan, S., Narasimhan, G., Gettle, R., Kapre, R., Sharifzadeh, S.
Format Conference Proceeding
LanguageEnglish
Published Piscataway NJ IEEE 2004
Subjects
Annealing
Applied sciences
CMOS process
Costs
Design. Technologies. Operation analysis. Testing
Dielectrics
Electrodes
Electronics
Etching
Exact sciences and technology
Implants
Integrated circuits
Oxidation
Plasma temperature
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
Parasitic resistance
Trench technology
Complementary MOS technology
Cost lowering
Self aligned technology
Insulation technology
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Summary:A novel CMOS process architecture comprising of 1.5 nm equivalent oxide thickness (EOT) oxide/nitride (O/N) gate dielectric, self aligned shallow trench isolation (SASTI), dual poly/W gate and W cladded source/drain is shown to have low gate dielectric leakage with excellent boron blocking, no dopant cross-diffusion and lower gate and source/drain parasitic resistance.
ISBN:0780386841
9780780386846
DOI:10.1109/IEDM.2004.1419256