A low power MASH digital delta-sigma modulator with accurate output average value

• Published in: Microelectronics Vol. 121; p. 105381
• Main Authors: Mohammadi, Ismail, Sobhi, Jafar, Khiavi, Abdolhamid Moallemi, Koozehkanani, Ziaddin Daie
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.03.2022
• Subjects: Digital delta-sigma modulator (DDSM); Fractional-N frequency synthesizer; Multi-stage noise shaping (MASH); Multi-stage noise shaping (MASH); Digital delta-sigma modulator (DDSM); Fractional-N frequency synthesizer
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2022.105381

This paper presents a modified Multi-stAge noise Shaping (MASH) digital delta-sigma modulator (DDSM). The proposed structure has an accurate mean value and efficient randomization for all input values to reduce the spurious tones. In addition, the proposed MASH based Sigma Delta modulator has less hardware complexity and power consumption compared to conventional structures. The Verilog HDL-based simulations and experimental implementation on FPGA have been used to verify the randomization efficiency of the proposed structure. Power consumption and hardware complexity are verified by post-synthesis simulations. The randomization efficiency of the proposed MASH DDSM is also verified by phase noise simulation of the fractional-N frequency synthesizer.