A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations

• Published in: Microelectronics Vol. 144; p. 106087
• Main Authors: Dai, Chenghu, Ren, Zihua, Guan, Lijun, Liu, Haitao, Gao, Mengya, Lu, Wenjuan, Pang, Zhiyong, Peng, Chunyu, Wu, Xiulong
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.02.2024
• Subjects: In-memory computing; Logic operation; Multiply-and-accumulate; SRAM; von Neumann bottleneck; von Neumann bottleneck; In-memory computing; Logic operation; Multiply-and-accumulate; SRAM
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2023.106087

Artificial intelligence algorithms play important roles in image classification to speech recognition, which contains enormous Boolean logic and multiplication operations. Traditional von Neumann architecture separates computing and storage units, which leads to “power walls” and “memory walls” problems. In-memory computing (IMC) is a promising method to solve these problems. In this work, we propose an IMC macro based on customed 9T-SRAM, which can be configured in memory, Boolean logic and multiply-and-accumulate (MAC) modes. The 9T-SRAM adopts read/write decoupled and a tail transistor structure, which enhances the read stability and reduces power consumption. With the bias rows, Boolean logic results are obtained from the differential voltages on two bitlines, reducing the peripheral circuit for reference voltage generation. Furthermore, the bias rows replace analog to digital converter (ADC) to binarize the MAC result, reducing the area overhead. In a 55 nm process, simulations manifest the 9T-SRAM shows enhanced read static noise margin, and the macro exhibits stable IMC operations and high energy-efficiency.