2 Lanes × 2.65-6.4 Gb/s Scalable IO Transceiver with Delay Compensation Technique in 65 nm CMOS Process

• Published in: Journal of semiconductor technology and science Vol. 24; no. 3; pp. 184 - 190
• Main Authors: Chung, Goohyung, Cho, Kyoungub, Oh, Taehyoun
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.06.2024
• Subjects: 전기공학; scalable; CMOS; pre-emphasis; delay compensation; FIR driver; IO transceiver

A Delay compensation technique for implementing scalable high-speed logics has been proposed and its theoretical background has been analyzed fundamentally. Based on the scalable design methodology, the whole logics of proposed 2-channel transceiver operate successfully over the range of 2.65-6.4 Gb...