2 Lanes × 2.65-6.4 Gb/s Scalable IO Transceiver with Delay Compensation Technique in 65 nm CMOS Process

A Delay compensation technique for implementing scalable high-speed logics has been proposed and its theoretical background has been analyzed fundamentally. Based on the scalable design methodology, the whole logics of proposed 2-channel transceiver operate successfully over the range of 2.65-6.4 Gb...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 24; no. 3; pp. 184 - 190
Main Authors Chung, Goohyung, Cho, Kyoungub, Oh, Taehyoun
Format Journal Article
LanguageEnglish
Published 대한전자공학회 01.06.2024
Subjects
전기공학
scalable
CMOS
pre-emphasis
delay compensation
FIR driver
IO transceiver
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Summary:A Delay compensation technique for implementing scalable high-speed logics has been proposed and its theoretical background has been analyzed fundamentally. Based on the scalable design methodology, the whole logics of proposed 2-channel transceiver operate successfully over the range of 2.65-6.4 Gb/s. The prototype chip has been fabricated in 65 nm CMOS process and occupies 1.02 mm2 die area. The transceiver consumes 72 mW/lane from 1.2 V supply. The measured eye-openings show 28.7% improvement vertically in Tx output by pre-emphasis at 6.4 Gb/s. The built-in Rx BER counter shows 0.25 unit interval (UI) horizontal eye-opening improvement at 10-9 BER in this speed. KCI Citation Count: 0
ISSN:1598-1657
2233-4866
2233-4866
1598-1657
DOI:10.5573/JSTS.2024.24.3.184