Planar-Nanostrip-Channel InAlN/GaN HEMTs on Si With Improved } and } Linearity

• Published in: IEEE electron device letters Vol. 38; no. 5; pp. 619 - 622
• Main Authors: Weichuan Xing, Zhihong Liu, Haodong Qiu, Geok Ing Ng, Palacios, Tomas
• Format: Journal Article
• Language: English
• Published: IEEE 01.05.2017
• Subjects: Gallium nitride; GaN; HEMTs; high electron mobility transistor (HEMT); Linearity; Logic gates; MODFETs; Nanoscale devices; nanostrip; nanowire; Resistance
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2017.2689810

In this letter, we report an InAlN/GaN high electron mobility transistor (HEMT) with a planar nanostrip channel design to improve its transconductance g m and cutoff frequency f T linearity. The planar nanostrips were formed by partial arsenic ion implantation isolation in the channel under the gate. Devices with a gate length (L g ) of 80 nm and a source-to-drain distance (L sd ) of 1 μm were fabricated. A conventional device and a device with a fin-like nanowire channel were also fabricated together for comparison. It was observed that the nanostrip and nanowire channel structures can both suppress the access resistance increase at the high output current level, and thereby improve the device's g m and f T linearity. Compared to the one using etching to form a fin-like nanostrip channel, the GaN HEMT with a planar nanostrip channel has demonstrated reduced parasitic capacitance and improved RF performance.