Design and Analysis of 3D Integrated Folded Ferro-Capacitive Crossbar Array (FC²A) for Brain-Inspired Computing System

• Published in: IEEE journal on emerging and selected topics in circuits and systems Vol. 14; no. 3; pp. 563 - 574
• Main Authors: Thomas, Sherin A., Kushwaha, Suyash, Sharma, Rohit, Mrinal Das, Devarshi
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.09.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3D integrated circuit; Arrays; Brain; Circuits; CMOS; Computation; Computer architecture; Ferrocapacitive crossbar array; Impact analysis; in-memory computing; Integrated circuit interconnections; interconnect; Izhikevich neuron; neuromorphic system; Neurons; parasitic effects; Pattern analysis; Pattern recognition; Spiking; Synapses; System reliability; Three-dimensional displays
• ISSN: 2156-3357; 2156-3365
• DOI: 10.1109/JETCAS.2024.3432458

This paper presents a novel 3D folded capacitive synaptic crossbar array designed for in-memory computing architectures. In this architecture, the bitline is folded over the wordline to enhance the synaptic density. The proposed folded capacitive crossbar array (<inline-formula> <tex-math notation="LaTeX">FC^{2}A </tex-math></inline-formula>) architecture decreases the wordline interconnect length and physical crossbar area by 50%. Thus, it helps to reduce the crossbar-associated parasitics and optimize space utilization. The proposed folded capacitive synaptic crossbar is used for designing a brain-inspired computing system (BiCoS) to recognize different patterns using CMOS technology. The BiCoS systems are prone to various reliability issues caused by the crossbar's parasitics. Hence, the 3D folded capacitive crossbar's Q3D model is developed to investigate the crossbar-associated parasitics and its effect on the proposed system is analyzed. The impact of crossbar parasitics is investigated for two cases: Firstly, how the three different spiking patterns (regular spiking, fast-spiking, and chattering) of the Izhikevich neuron change for the different crossbar sizes. Secondly, the impact is analyzed on the pattern recognition rate, which gets reduced to 70%. Addressing these challenges is critical to ensure the correct and robust working of the proposed system. Therefore, we propose a solution to effectively overcome and resolve these adverse effects. The energy consumed to recognize each pattern is calculated, and the average energy needed is <inline-formula> <tex-math notation="LaTeX">0.25\,nJ </tex-math></inline-formula>, which is significantly less when compared to the other state-of-the-art works. The circuit is implemented using 65nm standard CMOS technology.