Charge Pumping in Ultrathin SOI Tunnel FETs: Impact of Back-Gate Voltage

A thorough investigation of trap density (Dit) at the interfaces of FD-SOI Tunnel FET (TFET) devices is presented. Charge pumping (CP) method confirms a larger average defect concentration at the top interface of Low-Temperature processed TFETs than in devices made using a standard high-temperature...

Full description

Saved in:
Bibliographic Details
Published inECS transactions Vol. 89; no. 3; pp. 111 - 120
Main Authors Diaz Llorente, Carlos, G. Theodorou, Christoforos, Colinge, Jean-Pierre, Cristoloveanu, Sorin, Martinie, Sebastien, Le Royer, Cyrille, Ghibaudo, Gerard, Vinet, Maud
Format Journal Article
LanguageEnglish
Published The Electrochemical Society, Inc 23.04.2019
Electrochemical Society, Inc
Subjects
Data Analysis, Statistics and Probability
Electronics
Engineering Sciences
Micro and nanotechnologies
Microelectronics
Physics
Online AccessGet full text

Cover

More Information
Summary:A thorough investigation of trap density (Dit) at the interfaces of FD-SOI Tunnel FET (TFET) devices is presented. Charge pumping (CP) method confirms a larger average defect concentration at the top interface of Low-Temperature processed TFETs than in devices made using a standard high-temperature process. Back-gate bias is used to avoid probing the back-interface traps. We demonstrate the link between the CP current (experiments) and the carrier concentration (TCAD) at the interfaces during measurement. Simulation results demonstrate that the unusual variation of CP current in ultrathin FD-SOI depends on the carriers available for recombination at both front and back interfaces.
ISSN:1938-5862
1938-6737
1938-6737
1938-5862
DOI:10.1149/08903.0111ecst