A 2-GHz Two-Tone Direct Digital Frequency Synthesizer

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 69; no. 12; pp. 5109 - 5113
• Main Authors: Narayan Sinha, Shibendra, Chatterjee, Shouri, Palani, Rakesh Kumar
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: direct digital synthesis; Field programmable gate array; Field programmable gate arrays; frequency; Frequency division multiplexing; Frequency synthesizers; lookup table; Multicore processing; Pipeline processing; Synthesis; Table lookup; Time-frequency analysis; Truncation errors
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2022.3202903

We present a 2-GHz 16-bit direct digital synthesizer (DDS) implemented and verified on a Xilinx Artix-7 FPGA, Nexys-4 DDR development board. The lookup-table based DDS is implemented with the help of multiplexers in a tree structure. The proposed technique can operate at a high clock frequency of 250 MHz and has no truncation error. The proposed DDS is also capable of producing two tones separated by a frequency resolution of 1/1024 times the clock frequency. Further, the tones can be backed off in approximately one dB step from full scale to −96 dB. The back-off is implemented without performing any real multiplication thereby increasing the throughput. 16 such parallel DDS slices are implemented to produce very high-frequency digital sinusoids. The design uses 3095 LUTs, 3465 flip flops, and 18 Block-RAMs for producing two tone output at 2GHz for a given back-off.