A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 71; no. 11; pp. 4961 - 4972
• Main Authors: Wang, Chua-Chin, Chodisetti, L S S Pavan Kumar, Ke, Jhih-Ying, Lo, Cheng-Yao, Lee, Tzung-Je, Tolentino, Lean Karlo Santos
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Buffers; Circuit reliability; Circuits; CMOS; Data transfer (computers); Detectors; duty cycle; FinFET; FinFETs; genetic algorithm; Genetic algorithms; I/O buffer; Mathematical models; PVT variation; Signal quality; Slew rate; Threshold voltage; Transistors
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2024.3419020

This paper presents a novel 6-Gbps variation insensitive input/output (I/O) buffer designed for DDR4 and DDR5 SDRAM data transfer in a 16-nm FinFET CMOS process. Utilizing genetic algorithm (GA) to model process, voltage, and temperature (PVT) variations, the study reveals insights into temperature and voltage effects on FinFET-based, nanoscale buffer characteristics, leading to the removal of the temperature detector circuit to save power and area. Voltage variations, however, significantly impact slew rate, prompting the introduction of a Voltage Detector circuit using ultra-low threshold voltage (ULVT) transistors. Innovative Voltage Level Converter, Pre-Driver, and Digital Logic Control circuits enhance slew rate and throughput while stabilizing the output signal quality. This results in reliable operation at 6.0 Gbps with improved slew rate (17.7%/39.75% for VDDIO =0.8/1.2 V) and duty cycle performance (50.5%/51.4% for VDDIO =0.8/1.2 V) due to PV auto-adjustment; the first in the world. The proposed design effectively addresses the stringent slew rate and data rate requirements of DDR4 and DDR5 SDRAMs, offering advancements in speed, reliability, and efficiency amidst PV variations.