A 250 MS/s 65.8-dB SNDR SAR ADC With Cross-Phase Common-Mode Feedback and Reconfigurable Inverter-Based Preamplifier in 28-nm CMOS

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 69; no. 12; pp. 4674 - 4678
• Main Authors: Yao, Bingbing, Qiu, Lei
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; Analog-digital conversion; Analog-to-digital converter (ADC); Bandwidth; Calibration; CMOS; common mode feedback (CMFB); comparator; Comparators; Electric potential; Feedback; Inverters; Power consumption; preamplifier; Preamplifiers; Reconfiguration; Recovery time; Registers; Sampling; successive-approximation-register (SAR); Switches; Timing; Voltage
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2022.3196156

This brief presents a 250 MS/s 12b successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The inverter-based preamplifier is introduced to suppress comparator noise. To improve the ADC robustness and speed, first, a cross-phase common mode feedback which explores the common mode voltage during the sampling phase, is proposed to address the PVT and input common mode voltage sensitivity of the inverter-based preamplifier. Second, a reconfigurable method is proposed to eliminate the long recovery time of the preamplifier at large input signals, as well as reduce the kickback noise at small input signals. Third, a PMOS pair with deliberate timing is introduced to accelerate the comparator regeneration without deteriorating its noise. The ADC employs 360 fF/side sampling capacitance and takes 2 ns conversion time to resolve 15 raw bits. Fabricated in 28 nm CMOS, the prototype ADC achieves 65.8 dB SNDR and 80.9 dB SFDR for a near-Nyquist input, occupies an active area of 0.01 mm2 and consumes a power of 4.7 mW, resulting in a Walden FOMW of 11.8 fJ/conv-step and a Schreier <inline-formula> <tex-math notation="LaTeX">{\mathrm {FOM}}_{{\boldsymbol{S}}} </tex-math></inline-formula> of 170.0 dB, respectively. Last but not least, the ADC attains a rail-to-rail input CM range.