0.5-V Low- V CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

A novel low-V T CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a conventiona...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 45; no. 11; pp. 2348 - 2355
Main Authors Kotabe, Akira, Yanagawa, Yoshimitsu, Akiyama, Satoru, Sekiguchi, Tomonori
Format Journal Article
LanguageEnglish
Published IEEE 01.11.2010
Subjects
CMOS integrated circuits
DRAM
Latches
Logic gates
low voltage
MOS devices
Power demand
preamplifier
Random access memory
sense amplifier (SA)
Sensors
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Summary:A novel low-V T CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a conventional preamplifier. By activating the proposed preamplifier temporarily during the write cycle, the writing time was 16.3 ns, which is 72% shorter than the case without activation of the proposed preamplifier, and this time is short enough to apply a DRAM array using the proposed preamplifier to 1.6-Gbit/s/pin DDR3 SDRAM. The operating current of the memory array and its peripheral circuit including the proposed preamplifier was reduced by 12% by reducing the data-line voltage from 0.8 to 0.5 V.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2010.2065650