Quantitative characterization of the software layer of a HW/SW co-designed processor

• Published in: 2016 IEEE International Symposium on Workload Characterization (IISWC) pp. 1 - 10
• Main Authors: Cano, Jose, Kumar, Rakesh, Brankovic, Aleksandar, Pavlou, Demos, Stavrouz, Kyriakos, Gibert, Enric, Martınez, Alejandro, Gonzalez, Antonio
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2016
• Subjects: Benchmark testing; Computer architecture; Hardware; Optimization; Registers; Software; Timing
• DOI: 10.1109/IISWC.2016.7581274

HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary translation and applies aggressive optimizations through exploiting the runtime application behavior, these hybrid architectures provide better performance/watt. However, a poorly designed software layer can result in significant translation/optimization overheads that may offset its benefits. This work presents a detailed characterization of the software layer of a HW/SW co-designed processor using a variety of benchmark suites. We observe that the performance of the software layer is very sensitive to the characteristics of the emulated application with a variance of more than 50%. We also show that the interaction between the software layer and the emulated application, while sharing the microarchitectural resources, can have 0-20% impact on performance. Finally, we identify some key elements which should be further investigated to reduce the observed variations in performance. The paper provides critical insights to improve the software layer design.