Challenges for Sige Bicmos in Advanced-Node SOI

A 45nm BiCMOS process, based on PDSOI CMOS, with SiGe HBT NPNs having f T / f MAX = 380/550GHz is presented. The bipolars are integrated on a PDSOI wafer in an epitaxial region above the handle wafer to avoid self-heating concerns. The paper reviews advantages and challenges to integrating SiGe BiCM...

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Bibliographic Details
Published inECS transactions Vol. 109; no. 4; pp. 141 - 149
Main Authors Pekarik, Jack, Jain, Vibhor, Kenney, Crystal, Holt, Judson, Khokale, Shweta, Saroop, Sudesh, Johnson, Jeffrey, Stein, Kenneth, Ontalus, Viorel, Durcan, Christopher, Nafari, Mona, Nesheiwat, Tayel, Saudari, Sangameshwar, Yarmoghaddam, Elahe, Chaurasia, Saloni, Joseph, Alvin
Format Journal Article
LanguageEnglish
Published The Electrochemical Society, Inc 30.09.2022
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Summary:A 45nm BiCMOS process, based on PDSOI CMOS, with SiGe HBT NPNs having f T / f MAX = 380/550GHz is presented. The bipolars are integrated on a PDSOI wafer in an epitaxial region above the handle wafer to avoid self-heating concerns. The paper reviews advantages and challenges to integrating SiGe BiCMOS on an advanced node SOI technology.
ISSN:1938-5862
1938-6737
DOI:10.1149/10904.0141ecst