An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell

The key technology for achieving the low-voltage operation is shown to be a polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is successfully stacked on the bulk MOSFET, using 0.5- mu m CMOS technology. The investigation emphasizes the soft error rate (SER) and the stability of the cell....

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 25; no. 1; pp. 55 - 60
Main Authors Ishibashi, K., Yamanaka, T., Shimohigashi, K.
Format Journal Article
LanguageEnglish
Published IEEE 01.02.1990
Subjects
Capacitors
CMOS technology
Electrodes
Error analysis
Low voltage
MOS devices
MOSFET circuits
Power MOSFET
Random access memory
Stability
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Summary:The key technology for achieving the low-voltage operation is shown to be a polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is successfully stacked on the bulk MOSFET, using 0.5- mu m CMOS technology. The investigation emphasizes the soft error rate (SER) and the stability of the cell. The SER of the PPL cell at a supply voltage of 2 V is comparable to that of the conventional high-resistivity polysilicon load cell at a supply voltage of 5 V. The cell stability is also improved using a PPL cell, so that the low-voltage operation is assured.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.50284